A number of two wire bi-directional signal transmission systems have been extensively used. One such system is the Inter Integrated Circuit Bus system (I2C Bus system), disclosed in the Philips Data Handbook IC12a, 1989, and “The I2C Bus and how to use it (including specifications)” 1995 Philips Semiconductors.
The I2C Bus system is a serial bus system between individual integrated circuits, or stations, that are interconnected through a bi-directional two wire transmission channel. Of the two wires, one carries a clock signal, and the other the data, with a predetermined communication protocol. Depending on the particular function within the system, an individual station can act as the transmitter, or as a receiver. In many cases the full bi-directional capability is not used, and presents unnecessary complexity to fully meet all aspects of the I2C system standards, even when these features are not used or needed in many specific applications.
The I2C system uses a data wire (SDA) and clock wire (SCL) which are connected to a positive supply (VCC) through pull-up resistors. When the stations are not communicating the clock and data lines are free, and pulled high by these resistors. Each station which can communicate on the bus has an open collector or open drain output which can pull the bus lines to a low voltage level close to the negative supply (VEE). The sequence in which the SCL and SDA lines are pulled low provides the communication information flow between the integrated circuits sharing that bus.
The number of stations allowed, or the distance over which the bus can communicate is determined by the load presented on the bus line by the total capacitance of each line. That is by the total of the capacitance of the bus wiring, the connections, the integrated circuit pins, and the capacitive load presented by each input/output circuit within the integrated circuit. If the bus capacitance is increased then the maximum possible speed of the bus is limited, and the slower rise times on the bus start to cause difficulties.
The I2C Bus was designed to allow communication of data between integrated circuits on a single assembled printed circuit board in a manner which does not require a wide communication bus or individual address lines between ICs in order to achieve that communication. However designers quickly became aware that the advantages offered by I2C interconnection between circuits within a single board assembly, would also be available if the bus could be used to communicate over greater distances. In other applications, as the complexity of the system increased, many examples were found which required more than the maximum number of integrated circuits permitted by the specification to share the bus.
For example, in a digital voltmeter, the communication between the parts of the circuit performing range switching, the measuring circuit, the controller, the measurement memory, and the display drive was traditionally designed with multiple wire parallel buses between each integrated circuit used to construct the meter. This presents a challenge to design an efficient printed circuit layout with so many interconnections on the circuit board. Much of the complexity is because it requires parallel bus pins on each IC to accommodate all of these interconnections. In this example, the communication between each block in the circuit does not need high speed communication in real time, and the two wire I2C bus offered an opportunity of providing all of the data communication with only the two bus wires (the SCL clock, and SDA data lines) which make up the common bus connected in common to each I2C enabled integrated circuit in the system.
Also evident in this example, is that much of the communication does not need to be fully bi-directional. It does not need the multi-master or clock pulse stretching capability defined by the full I2C bus specification. Thus a design may be needed for a meter to drive a remote display. The increased distance to the display increases the capacitance of the connecting wires, and to meet the I2C loading limit, it is appropriate to use bus buffers to enable the signal to be transmitted over the increased distance. But a display needs no reverse signal path, and could use a buffer which does not offer the full bi-directional capability.
A number of design suggestions have been made to overcome these problems of expanding and extending the application of the I2C Bus. Many simple circuits have been published seeking to provide this expanded capability. Most of these circuits have problems which may be associated with latching, be only conditionally stable, or present glitches. The usual limitation presented by such circuits is that they are unable to reverse their direction of signal flow when active, generating a glitch that can upset the bus I2C function. For example a circuit will latch if the receiving logic path goes low and transfers this input low to the output. If this low output is detected as being low and transmitted back along the return path, then this low signal returning to the input as a low will hold the input low, even when the original external low drive signal is removed. Thus the bus has ‘latched’ into this low state. To prevent latching, various circuit techniques have been suggested to break that loop, and yet to still fulfil the required function. Oscillation in such a loop then becomes another possible problem.
A more subtle problem arises because the I2C Bus protocol has been defined so that two or more ICs may transmit (that is pull the I2C bus low) at the same time. With all ICs connected to the bus monitoring the bus line voltage, including the two or more which have started transmitting. The two active ICs contend, or compete to obtain control of the bus. This is called bus contention. As soon as one of those transmitting ICs detects that the bus has remained LOW even when that IC is attempting to transmit a HIGH signal, then that IC will immediately stop transmitting. That is when it detects the LOW being transmitted by another IC, when it was attempting to send a HIGH it stops transmitting and waits to retry at a later opportunity when hopefully there will be no contention.
A problem with many prior art circuits claimed to be able to provide a suitable buffering action is a problem that arises during bus contention. The way these circuits operate is to buffer the contending signals in a manner that generates spurious signals. To demonstrate this, consider when one side of the buffer circuit is held low, and while that input side is still held low, another integrated circuit connected to the buffer output generates a low signal. When the original input drive is released, the action of the buffer should be able to detect the application of the low on the output side, and continue to hold the original input side bus low even when the input drive signal ceases. However in circuits of the prior art there is a delay between the time the active forward path switches off, and the time when the reverse path is activated. This results in the input pin briefly being pulled high during this delay while the buffer signal path reverses, thereby generating a glitch which can be falsely interpreted by the integrated circuits connected on the input side as a signal pulse. A test for correct behaviour in these circumstances is called a glitch test. Many prior art circuits fail this test, whereby the input goes high for the time needed for the buffer circuit to recognise that the signal path has reversed.
The problem arises during the sort of pulse sequence which might occur during bus arbitration when there is a signal contention. In this test when the input to the bus is pulled LOW, the output side of the buffer circuit follows and goes LOW. If the output is then held LOW by another IC pulling it LOW on the output side (it is already being held LOW at that time, being held LOW by the original input signal acting via the forward path through the buffer). Then when an external LOW is applied to the output side of the buffer it will be held LOW by both the input being LOW, and the output being held LOW by the external signal as well. If the input LOW is then released, and we observe the behaviour of the input pin voltage after it is released by watching the voltage on the input side, we should observe it remaining LOW because the output is still being held LOW. However in prior art buffer circuits the forward path from input to output is active until after the input LOW is released, and the reverse path only becomes active when the forward path is switched off. To prevent latching this active path has locked out the reverse path from the output back to the input side of the buffer. So when the input drive holding the input LOW is released, the input pin will initially go HIGH to turn off the forward signal path, and only after the time delay for this signal to propagate to the output, will the externally applied LOW on the output be detected, and the reverse path from output to input enabled, so that, after a further propagation delay, the input pin is pulled back LOW again to reflect the LOW at the output pin. This HIGH pulse which appears on the input pin when it is released, appears as an unwelcome glitch until the LOW signal from the output is propagated back to the input and able to pull it low. This glitch can present a HIGH signal to the ICs on the bus at a time when the bus should be held LOW without a glitch.
The I2C specification does allow glitches of less than a specified duration at non critical times. However a glitch on the SCL, or clock line may be interpreted as a clock pulse, and will generate a spurious signal at the receiver, something that cannot be tolerated.
In all of these examples the circuitry needed to avoid generating a glitch on reversal of the signal path adds to the complexity and also limits the maximum speed of the circuit. The added complexity adds significantly to its cost.
It is an object of this invention to provide a cost-effective solution to the problems of the prior art, or at least to offer the public a useful alternative.
It is an object of this invention to provide a simple circuit, preferably at a lower cost which includes the possible generation of a glitch at times where its presence would not cause a problem.